AVR Libc Home Page AVRs AVR Libc Development Pages
Main Page User Manual Library Reference FAQ Alphabetical Index Example Projects

boot.h

Go to the documentation of this file.
00001 /* Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009  Eric B. Weddington
00002    All rights reserved.
00003 
00004    Redistribution and use in source and binary forms, with or without
00005    modification, are permitted provided that the following conditions are met:
00006 
00007    * Redistributions of source code must retain the above copyright
00008      notice, this list of conditions and the following disclaimer.
00009    * Redistributions in binary form must reproduce the above copyright
00010      notice, this list of conditions and the following disclaimer in
00011      the documentation and/or other materials provided with the
00012      distribution.
00013    * Neither the name of the copyright holders nor the names of
00014      contributors may be used to endorse or promote products derived
00015      from this software without specific prior written permission.
00016 
00017   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00018   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00019   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00020   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
00021   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00022   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00023   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00024   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00025   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00026   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00027   POSSIBILITY OF SUCH DAMAGE. */
00028 
00029 /* $Id: boot.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */
00030 
00031 #ifndef _AVR_BOOT_H_
00032 #define _AVR_BOOT_H_    1
00033 
00034 /** \file */
00035 /** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities
00036     \code
00037     #include <avr/io.h>
00038     #include <avr/boot.h>
00039     \endcode
00040 
00041     The macros in this module provide a C language interface to the
00042     bootloader support functionality of certain AVR processors. These
00043     macros are designed to work with all sizes of flash memory.
00044 
00045     Global interrupts are not automatically disabled for these macros. It
00046     is left up to the programmer to do this. See the code example below. 
00047     Also see the processor datasheet for caveats on having global interrupts 
00048     enabled during writing of the Flash.
00049 
00050     \note Not all AVR processors provide bootloader support. See your
00051     processor datasheet to see if it provides bootloader support.
00052 
00053     \todo From email with Marek: On smaller devices (all except ATmega64/128),
00054     __SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
00055     instructions - since the boot loader has a limited size, this could be an
00056     important optimization.
00057 
00058     \par API Usage Example
00059     The following code shows typical usage of the boot API.
00060 
00061     \code
00062     #include <inttypes.h>
00063     #include <avr/interrupt.h>
00064     #include <avr/pgmspace.h>
00065     
00066     void boot_program_page (uint32_t page, uint8_t *buf)
00067     {
00068         uint16_t i;
00069         uint8_t sreg;
00070 
00071         // Disable interrupts.
00072 
00073         sreg = SREG;
00074         cli();
00075     
00076         eeprom_busy_wait ();
00077 
00078         boot_page_erase (page);
00079         boot_spm_busy_wait ();      // Wait until the memory is erased.
00080 
00081         for (i=0; i<SPM_PAGESIZE; i+=2)
00082         {
00083             // Set up little-endian word.
00084 
00085             uint16_t w = *buf++;
00086             w += (*buf++) << 8;
00087         
00088             boot_page_fill (page + i, w);
00089         }
00090 
00091         boot_page_write (page);     // Store buffer in flash page.
00092         boot_spm_busy_wait();       // Wait until the memory is written.
00093 
00094         // Reenable RWW-section again. We need this if we want to jump back
00095         // to the application after bootloading.
00096 
00097         boot_rww_enable ();
00098 
00099         // Re-enable interrupts (if they were ever enabled).
00100 
00101         SREG = sreg;
00102     }\endcode */
00103 
00104 #include <avr/eeprom.h>
00105 #include <avr/io.h>
00106 #include <inttypes.h>
00107 #include <limits.h>
00108 
00109 /* Check for SPM Control Register in processor. */
00110 #if defined (SPMCSR)
00111 #  define __SPM_REG    SPMCSR
00112 #elif defined (SPMCR)
00113 #  define __SPM_REG    SPMCR
00114 #else
00115 #  error AVR processor does not provide bootloader support!
00116 #endif
00117 
00118 
00119 /* Check for SPM Enable bit. */
00120 #if defined(SPMEN)
00121 #  define __SPM_ENABLE  SPMEN
00122 #elif defined(SELFPRGEN)
00123 #  define __SPM_ENABLE  SELFPRGEN
00124 #else
00125 #  error Cannot find SPM Enable bit definition!
00126 #endif
00127 
00128 /** \ingroup avr_boot
00129     \def BOOTLOADER_SECTION
00130 
00131     Used to declare a function or variable to be placed into a
00132     new section called .bootloader. This section and its contents
00133     can then be relocated to any address (such as the bootloader
00134     NRWW area) at link-time. */
00135 
00136 #define BOOTLOADER_SECTION    __attribute__ ((section (".bootloader")))
00137 
00138 /* Create common bit definitions. */
00139 #ifdef ASB
00140 #define __COMMON_ASB    ASB
00141 #else
00142 #define __COMMON_ASB    RWWSB
00143 #endif
00144 
00145 #ifdef ASRE
00146 #define __COMMON_ASRE   ASRE
00147 #else
00148 #define __COMMON_ASRE   RWWSRE
00149 #endif
00150 
00151 /* Define the bit positions of the Boot Lock Bits. */
00152 
00153 #define BLB12           5
00154 #define BLB11           4
00155 #define BLB02           3
00156 #define BLB01           2
00157 
00158 /** \ingroup avr_boot
00159     \def boot_spm_interrupt_enable()
00160     Enable the SPM interrupt. */
00161 
00162 #define boot_spm_interrupt_enable()   (__SPM_REG |= (uint8_t)_BV(SPMIE))
00163 
00164 /** \ingroup avr_boot
00165     \def boot_spm_interrupt_disable()
00166     Disable the SPM interrupt. */
00167 
00168 #define boot_spm_interrupt_disable()  (__SPM_REG &= (uint8_t)~_BV(SPMIE))
00169 
00170 /** \ingroup avr_boot
00171     \def boot_is_spm_interrupt()
00172     Check if the SPM interrupt is enabled. */
00173 
00174 #define boot_is_spm_interrupt()       (__SPM_REG & (uint8_t)_BV(SPMIE))
00175 
00176 /** \ingroup avr_boot
00177     \def boot_rww_busy()
00178     Check if the RWW section is busy. */
00179 
00180 #define boot_rww_busy()          (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
00181 
00182 /** \ingroup avr_boot
00183     \def boot_spm_busy()
00184     Check if the SPM instruction is busy. */
00185 
00186 #define boot_spm_busy()               (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
00187 
00188 /** \ingroup avr_boot
00189     \def boot_spm_busy_wait()
00190     Wait while the SPM instruction is busy. */
00191 
00192 #define boot_spm_busy_wait()          do{}while(boot_spm_busy())
00193 
00194 #define __BOOT_PAGE_ERASE         (_BV(__SPM_ENABLE) | _BV(PGERS))
00195 #define __BOOT_PAGE_WRITE         (_BV(__SPM_ENABLE) | _BV(PGWRT))
00196 #define __BOOT_PAGE_FILL          _BV(__SPM_ENABLE)
00197 #define __BOOT_RWW_ENABLE         (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
00198 #if defined(BLBSET)
00199 #define __BOOT_LOCK_BITS_SET      (_BV(__SPM_ENABLE) | _BV(BLBSET))
00200 #elif defined(RFLB)  /* Some devices have RFLB defined instead of BLBSET. */
00201 #define __BOOT_LOCK_BITS_SET      (_BV(__SPM_ENABLE) | _BV(RFLB))
00202 #endif
00203 
00204 #define __boot_page_fill_normal(address, data)   \
00205 (__extension__({                                 \
00206     __asm__ __volatile__                         \
00207     (                                            \
00208         "movw  r0, %3\n\t"                       \
00209         "sts %0, %1\n\t"                         \
00210         "spm\n\t"                                \
00211         "clr  r1\n\t"                            \
00212         :                                        \
00213         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00214           "r" ((uint8_t)(__BOOT_PAGE_FILL)),     \
00215           "z" ((uint16_t)(address)),             \
00216           "r" ((uint16_t)(data))                 \
00217         : "r0"                                   \
00218     );                                           \
00219 }))
00220 
00221 #define __boot_page_fill_alternate(address, data)\
00222 (__extension__({                                 \
00223     __asm__ __volatile__                         \
00224     (                                            \
00225         "movw  r0, %3\n\t"                       \
00226         "sts %0, %1\n\t"                         \
00227         "spm\n\t"                                \
00228         ".word 0xffff\n\t"                       \
00229         "nop\n\t"                                \
00230         "clr  r1\n\t"                            \
00231         :                                        \
00232         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00233           "r" ((uint8_t)(__BOOT_PAGE_FILL)),     \
00234           "z" ((uint16_t)(address)),             \
00235           "r" ((uint16_t)(data))                 \
00236         : "r0"                                   \
00237     );                                           \
00238 }))
00239 
00240 #define __boot_page_fill_extended(address, data) \
00241 (__extension__({                                 \
00242     __asm__ __volatile__                         \
00243     (                                            \
00244         "movw  r0, %4\n\t"                       \
00245         "movw r30, %A3\n\t"                      \
00246         "sts %1, %C3\n\t"                        \
00247         "sts %0, %2\n\t"                         \
00248         "spm\n\t"                                \
00249         "clr  r1\n\t"                            \
00250         :                                        \
00251         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00252           "i" (_SFR_MEM_ADDR(RAMPZ)),            \
00253           "r" ((uint8_t)(__BOOT_PAGE_FILL)),     \
00254           "r" ((uint32_t)(address)),             \
00255           "r" ((uint16_t)(data))                 \
00256         : "r0", "r30", "r31"                     \
00257     );                                           \
00258 }))
00259 
00260 #define __boot_page_erase_normal(address)        \
00261 (__extension__({                                 \
00262     __asm__ __volatile__                         \
00263     (                                            \
00264         "sts %0, %1\n\t"                         \
00265         "spm\n\t"                                \
00266         :                                        \
00267         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00268           "r" ((uint8_t)(__BOOT_PAGE_ERASE)),    \
00269           "z" ((uint16_t)(address))              \
00270     );                                           \
00271 }))
00272 
00273 #define __boot_page_erase_alternate(address)     \
00274 (__extension__({                                 \
00275     __asm__ __volatile__                         \
00276     (                                            \
00277         "sts %0, %1\n\t"                         \
00278         "spm\n\t"                                \
00279         ".word 0xffff\n\t"                       \
00280         "nop\n\t"                                \
00281         :                                        \
00282         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00283           "r" ((uint8_t)(__BOOT_PAGE_ERASE)),    \
00284           "z" ((uint16_t)(address))              \
00285     );                                           \
00286 }))
00287 
00288 #define __boot_page_erase_extended(address)      \
00289 (__extension__({                                 \
00290     __asm__ __volatile__                         \
00291     (                                            \
00292         "movw r30, %A3\n\t"                      \
00293         "sts  %1, %C3\n\t"                       \
00294         "sts %0, %2\n\t"                         \
00295         "spm\n\t"                                \
00296         :                                        \
00297         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00298           "i" (_SFR_MEM_ADDR(RAMPZ)),            \
00299           "r" ((uint8_t)(__BOOT_PAGE_ERASE)),    \
00300           "r" ((uint32_t)(address))              \
00301         : "r30", "r31"                           \
00302     );                                           \
00303 }))
00304 
00305 #define __boot_page_write_normal(address)        \
00306 (__extension__({                                 \
00307     __asm__ __volatile__                         \
00308     (                                            \
00309         "sts %0, %1\n\t"                         \
00310         "spm\n\t"                                \
00311         :                                        \
00312         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00313           "r" ((uint8_t)(__BOOT_PAGE_WRITE)),    \
00314           "z" ((uint16_t)(address))              \
00315     );                                           \
00316 }))
00317 
00318 #define __boot_page_write_alternate(address)     \
00319 (__extension__({                                 \
00320     __asm__ __volatile__                         \
00321     (                                            \
00322         "sts %0, %1\n\t"                         \
00323         "spm\n\t"                                \
00324         ".word 0xffff\n\t"                       \
00325         "nop\n\t"                                \
00326         :                                        \
00327         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00328           "r" ((uint8_t)(__BOOT_PAGE_WRITE)),    \
00329           "z" ((uint16_t)(address))              \
00330     );                                           \
00331 }))
00332 
00333 #define __boot_page_write_extended(address)      \
00334 (__extension__({                                 \
00335     __asm__ __volatile__                         \
00336     (                                            \
00337         "movw r30, %A3\n\t"                      \
00338         "sts %1, %C3\n\t"                        \
00339         "sts %0, %2\n\t"                         \
00340         "spm\n\t"                                \
00341         :                                        \
00342         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00343           "i" (_SFR_MEM_ADDR(RAMPZ)),            \
00344           "r" ((uint8_t)(__BOOT_PAGE_WRITE)),    \
00345           "r" ((uint32_t)(address))              \
00346         : "r30", "r31"                           \
00347     );                                           \
00348 }))
00349 
00350 #define __boot_rww_enable()                      \
00351 (__extension__({                                 \
00352     __asm__ __volatile__                         \
00353     (                                            \
00354         "sts %0, %1\n\t"                         \
00355         "spm\n\t"                                \
00356         :                                        \
00357         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00358           "r" ((uint8_t)(__BOOT_RWW_ENABLE))     \
00359     );                                           \
00360 }))
00361 
00362 #define __boot_rww_enable_alternate()            \
00363 (__extension__({                                 \
00364     __asm__ __volatile__                         \
00365     (                                            \
00366         "sts %0, %1\n\t"                         \
00367         "spm\n\t"                                \
00368         ".word 0xffff\n\t"                       \
00369         "nop\n\t"                                \
00370         :                                        \
00371         : "i" (_SFR_MEM_ADDR(__SPM_REG)),        \
00372           "r" ((uint8_t)(__BOOT_RWW_ENABLE))     \
00373     );                                           \
00374 }))
00375 
00376 /* From the mega16/mega128 data sheets (maybe others):
00377 
00378      Bits by SPM To set the Boot Loader Lock bits, write the desired data to
00379      R0, write "X0001001" to SPMCR and execute SPM within four clock cycles
00380      after writing SPMCR. The only accessible Lock bits are the Boot Lock bits
00381      that may prevent the Application and Boot Loader section from any
00382      software update by the MCU.
00383 
00384      If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
00385      will be programmed if an SPM instruction is executed within four cycles
00386      after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is 
00387      don't care during this operation, but for future compatibility it is 
00388      recommended to load the Z-pointer with $0001 (same as used for reading the 
00389      Lock bits). For future compatibility It is also recommended to set bits 7, 
00390      6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the 
00391      Lock bits the entire Flash can be read during the operation. */
00392 
00393 #define __boot_lock_bits_set(lock_bits)                    \
00394 (__extension__({                                           \
00395     uint8_t value = (uint8_t)(~(lock_bits));               \
00396     __asm__ __volatile__                                   \
00397     (                                                      \
00398         "ldi r30, 1\n\t"                                   \
00399         "ldi r31, 0\n\t"                                   \
00400         "mov r0, %2\n\t"                                   \
00401         "sts %0, %1\n\t"                                   \
00402         "spm\n\t"                                          \
00403         :                                                  \
00404         : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
00405           "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)),           \
00406           "r" (value)                                      \
00407         : "r0", "r30", "r31"                               \
00408     );                                                     \
00409 }))
00410 
00411 #define __boot_lock_bits_set_alternate(lock_bits)          \
00412 (__extension__({                                           \
00413     uint8_t value = (uint8_t)(~(lock_bits));               \
00414     __asm__ __volatile__                                   \
00415     (                                                      \
00416         "ldi r30, 1\n\t"                                   \
00417         "ldi r31, 0\n\t"                                   \
00418         "mov r0, %2\n\t"                                   \
00419         "sts %0, %1\n\t"                                   \
00420         "spm\n\t"                                          \
00421         ".word 0xffff\n\t"                                 \
00422         "nop\n\t"                                          \
00423         :                                                  \
00424         : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
00425           "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)),           \
00426           "r" (value)                                      \
00427         : "r0", "r30", "r31"                               \
00428     );                                                     \
00429 }))
00430 
00431 /*
00432    Reading lock and fuse bits:
00433 
00434      Similarly to writing the lock bits above, set BLBSET and SPMEN (or 
00435      SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an 
00436      LPM instruction.
00437 
00438      Z address:       contents:
00439      0x0000           low fuse bits
00440      0x0001           lock bits
00441      0x0002           extended fuse bits
00442      0x0003           high fuse bits
00443 
00444      Sounds confusing, doesn't it?
00445 
00446      Unlike the macros in pgmspace.h, no need to care for non-enhanced
00447      cores here as these old cores do not provide SPM support anyway.
00448  */
00449 
00450 /** \ingroup avr_boot
00451     \def GET_LOW_FUSE_BITS
00452     address to read the low fuse bits, using boot_lock_fuse_bits_get
00453  */
00454 #define GET_LOW_FUSE_BITS           (0x0000)
00455 /** \ingroup avr_boot
00456     \def GET_LOCK_BITS
00457     address to read the lock bits, using boot_lock_fuse_bits_get
00458  */
00459 #define GET_LOCK_BITS               (0x0001)
00460 /** \ingroup avr_boot
00461     \def GET_EXTENDED_FUSE_BITS
00462     address to read the extended fuse bits, using boot_lock_fuse_bits_get
00463  */
00464 #define GET_EXTENDED_FUSE_BITS      (0x0002)
00465 /** \ingroup avr_boot
00466     \def GET_HIGH_FUSE_BITS
00467     address to read the high fuse bits, using boot_lock_fuse_bits_get
00468  */
00469 #define GET_HIGH_FUSE_BITS          (0x0003)
00470 
00471 /** \ingroup avr_boot
00472     \def boot_lock_fuse_bits_get(address)
00473 
00474     Read the lock or fuse bits at \c address.
00475 
00476     Parameter \c address can be any of GET_LOW_FUSE_BITS,
00477     GET_LOCK_BITS, GET_EXTENDED_FUSE_BITS, or GET_HIGH_FUSE_BITS.
00478 
00479     \note The lock and fuse bits returned are the physical values,
00480     i.e. a bit returned as 0 means the corresponding fuse or lock bit
00481     is programmed.
00482  */
00483 #define boot_lock_fuse_bits_get(address)                   \
00484 (__extension__({                                           \
00485     uint8_t __result;                                      \
00486     __asm__ __volatile__                                   \
00487     (                                                      \
00488         "sts %1, %2\n\t"                                   \
00489         "lpm %0, Z\n\t"                                    \
00490         : "=r" (__result)                                  \
00491         : "i" (_SFR_MEM_ADDR(__SPM_REG)),                  \
00492           "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)),           \
00493           "z" ((uint16_t)(address))                        \
00494     );                                                     \
00495     __result;                                              \
00496 }))
00497 
00498 /** \ingroup avr_boot
00499     \def boot_signature_byte_get(address)
00500 
00501     Read the Signature Row byte at \c address.  For some MCU types,
00502     this function can also retrieve the factory-stored oscillator
00503     calibration bytes.
00504 
00505     Parameter \c address can be 0-0x1f as documented by the datasheet.
00506     \note The values are MCU type dependent.
00507 */
00508 
00509 #define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
00510 
00511 #define boot_signature_byte_get(addr) \
00512 (__extension__({                      \
00513       uint8_t __result;                         \
00514       __asm__ __volatile__                      \
00515       (                                         \
00516         "sts %1, %2\n\t"                        \
00517         "lpm %0, Z" "\n\t"                      \
00518         : "=r" (__result)                       \
00519         : "i" (_SFR_MEM_ADDR(__SPM_REG)),       \
00520           "r" ((uint8_t)(__BOOT_SIGROW_READ)),  \
00521           "z" ((uint16_t)(addr))                \
00522       );                                        \
00523       __result;                                 \
00524 }))
00525 
00526 /** \ingroup avr_boot
00527     \def boot_page_fill(address, data)
00528 
00529     Fill the bootloader temporary page buffer for flash 
00530     address with data word. 
00531 
00532     \note The address is a byte address. The data is a word. The AVR 
00533     writes data to the buffer a word at a time, but addresses the buffer
00534     per byte! So, increment your address by 2 between calls, and send 2
00535     data bytes in a word format! The LSB of the data is written to the lower 
00536     address; the MSB of the data is written to the higher address.*/
00537 
00538 /** \ingroup avr_boot
00539     \def boot_page_erase(address)
00540 
00541     Erase the flash page that contains address.
00542 
00543     \note address is a byte address in flash, not a word address. */
00544 
00545 /** \ingroup avr_boot
00546     \def boot_page_write(address)
00547 
00548     Write the bootloader temporary page buffer 
00549     to flash page that contains address.
00550     
00551     \note address is a byte address in flash, not a word address. */
00552 
00553 /** \ingroup avr_boot
00554     \def boot_rww_enable()
00555 
00556     Enable the Read-While-Write memory section. */
00557 
00558 /** \ingroup avr_boot
00559     \def boot_lock_bits_set(lock_bits)
00560 
00561     Set the bootloader lock bits.
00562 
00563     \param lock_bits A mask of which Boot Loader Lock Bits to set.
00564 
00565     \note In this context, a 'set bit' will be written to a zero value.
00566     Note also that only BLBxx bits can be programmed by this command.
00567 
00568     For example, to disallow the SPM instruction from writing to the Boot
00569     Loader memory section of flash, you would use this macro as such:
00570 
00571     \code
00572     boot_lock_bits_set (_BV (BLB11));
00573     \endcode
00574 
00575     \note Like any lock bits, the Boot Loader Lock Bits, once set,
00576     cannot be cleared again except by a chip erase which will in turn
00577     also erase the boot loader itself. */
00578 
00579 /* Normal versions of the macros use 16-bit addresses.
00580    Extended versions of the macros use 32-bit addresses.
00581    Alternate versions of the macros use 16-bit addresses and require special
00582    instruction sequences after LPM.
00583 
00584    FLASHEND is defined in the ioXXXX.h file.
00585    USHRT_MAX is defined in <limits.h>. */ 
00586 
00587 #if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
00588     || defined(__AVR_ATmega323__)
00589 
00590 /* Alternate: ATmega161/163/323 and 16 bit address */
00591 #define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
00592 #define boot_page_erase(address)      __boot_page_erase_alternate(address)
00593 #define boot_page_write(address)      __boot_page_write_alternate(address)
00594 #define boot_rww_enable()             __boot_rww_enable_alternate()
00595 #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
00596 
00597 #elif (FLASHEND > USHRT_MAX)
00598 
00599 /* Extended: >16 bit address */
00600 #define boot_page_fill(address, data) __boot_page_fill_extended(address, data)
00601 #define boot_page_erase(address)      __boot_page_erase_extended(address)
00602 #define boot_page_write(address)      __boot_page_write_extended(address)
00603 #define boot_rww_enable()             __boot_rww_enable()
00604 #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
00605 
00606 #else
00607 
00608 /* Normal: 16 bit address */
00609 #define boot_page_fill(address, data) __boot_page_fill_normal(address, data)
00610 #define boot_page_erase(address)      __boot_page_erase_normal(address)
00611 #define boot_page_write(address)      __boot_page_write_normal(address)
00612 #define boot_rww_enable()             __boot_rww_enable()
00613 #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
00614 
00615 #endif
00616 
00617 /** \ingroup avr_boot
00618 
00619     Same as boot_page_fill() except it waits for eeprom and spm operations to
00620     complete before filling the page. */
00621 
00622 #define boot_page_fill_safe(address, data) \
00623 do { \
00624     boot_spm_busy_wait();                       \
00625     eeprom_busy_wait();                         \
00626     boot_page_fill(address, data);              \
00627 } while (0)
00628 
00629 /** \ingroup avr_boot
00630 
00631     Same as boot_page_erase() except it waits for eeprom and spm operations to
00632     complete before erasing the page. */
00633 
00634 #define boot_page_erase_safe(address) \
00635 do { \
00636     boot_spm_busy_wait();                       \
00637     eeprom_busy_wait();                         \
00638     boot_page_erase (address);                  \
00639 } while (0)
00640 
00641 /** \ingroup avr_boot
00642 
00643     Same as boot_page_write() except it waits for eeprom and spm operations to
00644     complete before writing the page. */
00645 
00646 #define boot_page_write_safe(address) \
00647 do { \
00648     boot_spm_busy_wait();                       \
00649     eeprom_busy_wait();                         \
00650     boot_page_write (address);                  \
00651 } while (0)
00652 
00653 /** \ingroup avr_boot
00654 
00655     Same as boot_rww_enable() except waits for eeprom and spm operations to
00656     complete before enabling the RWW mameory. */
00657 
00658 #define boot_rww_enable_safe() \
00659 do { \
00660     boot_spm_busy_wait();                       \
00661     eeprom_busy_wait();                         \
00662     boot_rww_enable();                          \
00663 } while (0)
00664 
00665 /** \ingroup avr_boot
00666 
00667     Same as boot_lock_bits_set() except waits for eeprom and spm operations to
00668     complete before setting the lock bits. */
00669 
00670 #define boot_lock_bits_set_safe(lock_bits) \
00671 do { \
00672     boot_spm_busy_wait();                       \
00673     eeprom_busy_wait();                         \
00674     boot_lock_bits_set (lock_bits);             \
00675 } while (0)
00676 
00677 #endif /* _AVR_BOOT_H_ */

Automatically generated by Doxygen 1.7.3 on Thu May 19 2011.