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00031 #ifndef _AVR_BOOT_H_
00032 #define _AVR_BOOT_H_ 1
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00104 #include <avr/eeprom.h>
00105 #include <avr/io.h>
00106 #include <inttypes.h>
00107 #include <limits.h>
00108
00109
00110 #if defined (SPMCSR)
00111 # define __SPM_REG SPMCSR
00112 #elif defined (SPMCR)
00113 # define __SPM_REG SPMCR
00114 #else
00115 # error AVR processor does not provide bootloader support!
00116 #endif
00117
00118
00119
00120 #if defined(SPMEN)
00121 # define __SPM_ENABLE SPMEN
00122 #elif defined(SELFPRGEN)
00123 # define __SPM_ENABLE SELFPRGEN
00124 #else
00125 # error Cannot find SPM Enable bit definition!
00126 #endif
00127
00128
00129
00130
00131
00132
00133
00134
00135
00136 #define BOOTLOADER_SECTION __attribute__ ((section (".bootloader")))
00137
00138
00139 #ifdef ASB
00140 #define __COMMON_ASB ASB
00141 #else
00142 #define __COMMON_ASB RWWSB
00143 #endif
00144
00145 #ifdef ASRE
00146 #define __COMMON_ASRE ASRE
00147 #else
00148 #define __COMMON_ASRE RWWSRE
00149 #endif
00150
00151
00152
00153 #define BLB12 5
00154 #define BLB11 4
00155 #define BLB02 3
00156 #define BLB01 2
00157
00158
00159
00160
00161
00162 #define boot_spm_interrupt_enable() (__SPM_REG |= (uint8_t)_BV(SPMIE))
00163
00164
00165
00166
00167
00168 #define boot_spm_interrupt_disable() (__SPM_REG &= (uint8_t)~_BV(SPMIE))
00169
00170
00171
00172
00173
00174 #define boot_is_spm_interrupt() (__SPM_REG & (uint8_t)_BV(SPMIE))
00175
00176
00177
00178
00179
00180 #define boot_rww_busy() (__SPM_REG & (uint8_t)_BV(__COMMON_ASB))
00181
00182
00183
00184
00185
00186 #define boot_spm_busy() (__SPM_REG & (uint8_t)_BV(__SPM_ENABLE))
00187
00188
00189
00190
00191
00192 #define boot_spm_busy_wait() do{}while(boot_spm_busy())
00193
00194 #define __BOOT_PAGE_ERASE (_BV(__SPM_ENABLE) | _BV(PGERS))
00195 #define __BOOT_PAGE_WRITE (_BV(__SPM_ENABLE) | _BV(PGWRT))
00196 #define __BOOT_PAGE_FILL _BV(__SPM_ENABLE)
00197 #define __BOOT_RWW_ENABLE (_BV(__SPM_ENABLE) | _BV(__COMMON_ASRE))
00198 #if defined(BLBSET)
00199 #define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(BLBSET))
00200 #elif defined(RFLB)
00201 #define __BOOT_LOCK_BITS_SET (_BV(__SPM_ENABLE) | _BV(RFLB))
00202 #endif
00203
00204 #define __boot_page_fill_normal(address, data) \
00205 (__extension__({ \
00206 __asm__ __volatile__ \
00207 ( \
00208 "movw r0, %3\n\t" \
00209 "sts %0, %1\n\t" \
00210 "spm\n\t" \
00211 "clr r1\n\t" \
00212 : \
00213 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00214 "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
00215 "z" ((uint16_t)(address)), \
00216 "r" ((uint16_t)(data)) \
00217 : "r0" \
00218 ); \
00219 }))
00220
00221 #define __boot_page_fill_alternate(address, data)\
00222 (__extension__({ \
00223 __asm__ __volatile__ \
00224 ( \
00225 "movw r0, %3\n\t" \
00226 "sts %0, %1\n\t" \
00227 "spm\n\t" \
00228 ".word 0xffff\n\t" \
00229 "nop\n\t" \
00230 "clr r1\n\t" \
00231 : \
00232 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00233 "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
00234 "z" ((uint16_t)(address)), \
00235 "r" ((uint16_t)(data)) \
00236 : "r0" \
00237 ); \
00238 }))
00239
00240 #define __boot_page_fill_extended(address, data) \
00241 (__extension__({ \
00242 __asm__ __volatile__ \
00243 ( \
00244 "movw r0, %4\n\t" \
00245 "movw r30, %A3\n\t" \
00246 "sts %1, %C3\n\t" \
00247 "sts %0, %2\n\t" \
00248 "spm\n\t" \
00249 "clr r1\n\t" \
00250 : \
00251 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00252 "i" (_SFR_MEM_ADDR(RAMPZ)), \
00253 "r" ((uint8_t)(__BOOT_PAGE_FILL)), \
00254 "r" ((uint32_t)(address)), \
00255 "r" ((uint16_t)(data)) \
00256 : "r0", "r30", "r31" \
00257 ); \
00258 }))
00259
00260 #define __boot_page_erase_normal(address) \
00261 (__extension__({ \
00262 __asm__ __volatile__ \
00263 ( \
00264 "sts %0, %1\n\t" \
00265 "spm\n\t" \
00266 : \
00267 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00268 "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
00269 "z" ((uint16_t)(address)) \
00270 ); \
00271 }))
00272
00273 #define __boot_page_erase_alternate(address) \
00274 (__extension__({ \
00275 __asm__ __volatile__ \
00276 ( \
00277 "sts %0, %1\n\t" \
00278 "spm\n\t" \
00279 ".word 0xffff\n\t" \
00280 "nop\n\t" \
00281 : \
00282 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00283 "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
00284 "z" ((uint16_t)(address)) \
00285 ); \
00286 }))
00287
00288 #define __boot_page_erase_extended(address) \
00289 (__extension__({ \
00290 __asm__ __volatile__ \
00291 ( \
00292 "movw r30, %A3\n\t" \
00293 "sts %1, %C3\n\t" \
00294 "sts %0, %2\n\t" \
00295 "spm\n\t" \
00296 : \
00297 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00298 "i" (_SFR_MEM_ADDR(RAMPZ)), \
00299 "r" ((uint8_t)(__BOOT_PAGE_ERASE)), \
00300 "r" ((uint32_t)(address)) \
00301 : "r30", "r31" \
00302 ); \
00303 }))
00304
00305 #define __boot_page_write_normal(address) \
00306 (__extension__({ \
00307 __asm__ __volatile__ \
00308 ( \
00309 "sts %0, %1\n\t" \
00310 "spm\n\t" \
00311 : \
00312 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00313 "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
00314 "z" ((uint16_t)(address)) \
00315 ); \
00316 }))
00317
00318 #define __boot_page_write_alternate(address) \
00319 (__extension__({ \
00320 __asm__ __volatile__ \
00321 ( \
00322 "sts %0, %1\n\t" \
00323 "spm\n\t" \
00324 ".word 0xffff\n\t" \
00325 "nop\n\t" \
00326 : \
00327 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00328 "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
00329 "z" ((uint16_t)(address)) \
00330 ); \
00331 }))
00332
00333 #define __boot_page_write_extended(address) \
00334 (__extension__({ \
00335 __asm__ __volatile__ \
00336 ( \
00337 "movw r30, %A3\n\t" \
00338 "sts %1, %C3\n\t" \
00339 "sts %0, %2\n\t" \
00340 "spm\n\t" \
00341 : \
00342 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00343 "i" (_SFR_MEM_ADDR(RAMPZ)), \
00344 "r" ((uint8_t)(__BOOT_PAGE_WRITE)), \
00345 "r" ((uint32_t)(address)) \
00346 : "r30", "r31" \
00347 ); \
00348 }))
00349
00350 #define __boot_rww_enable() \
00351 (__extension__({ \
00352 __asm__ __volatile__ \
00353 ( \
00354 "sts %0, %1\n\t" \
00355 "spm\n\t" \
00356 : \
00357 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00358 "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \
00359 ); \
00360 }))
00361
00362 #define __boot_rww_enable_alternate() \
00363 (__extension__({ \
00364 __asm__ __volatile__ \
00365 ( \
00366 "sts %0, %1\n\t" \
00367 "spm\n\t" \
00368 ".word 0xffff\n\t" \
00369 "nop\n\t" \
00370 : \
00371 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00372 "r" ((uint8_t)(__BOOT_RWW_ENABLE)) \
00373 ); \
00374 }))
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00392
00393 #define __boot_lock_bits_set(lock_bits) \
00394 (__extension__({ \
00395 uint8_t value = (uint8_t)(~(lock_bits)); \
00396 __asm__ __volatile__ \
00397 ( \
00398 "ldi r30, 1\n\t" \
00399 "ldi r31, 0\n\t" \
00400 "mov r0, %2\n\t" \
00401 "sts %0, %1\n\t" \
00402 "spm\n\t" \
00403 : \
00404 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00405 "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
00406 "r" (value) \
00407 : "r0", "r30", "r31" \
00408 ); \
00409 }))
00410
00411 #define __boot_lock_bits_set_alternate(lock_bits) \
00412 (__extension__({ \
00413 uint8_t value = (uint8_t)(~(lock_bits)); \
00414 __asm__ __volatile__ \
00415 ( \
00416 "ldi r30, 1\n\t" \
00417 "ldi r31, 0\n\t" \
00418 "mov r0, %2\n\t" \
00419 "sts %0, %1\n\t" \
00420 "spm\n\t" \
00421 ".word 0xffff\n\t" \
00422 "nop\n\t" \
00423 : \
00424 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00425 "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
00426 "r" (value) \
00427 : "r0", "r30", "r31" \
00428 ); \
00429 }))
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00453
00454 #define GET_LOW_FUSE_BITS (0x0000)
00455
00456
00457
00458
00459 #define GET_LOCK_BITS (0x0001)
00460
00461
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00463
00464 #define GET_EXTENDED_FUSE_BITS (0x0002)
00465
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00469 #define GET_HIGH_FUSE_BITS (0x0003)
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00482
00483 #define boot_lock_fuse_bits_get(address) \
00484 (__extension__({ \
00485 uint8_t __result; \
00486 __asm__ __volatile__ \
00487 ( \
00488 "sts %1, %2\n\t" \
00489 "lpm %0, Z\n\t" \
00490 : "=r" (__result) \
00491 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00492 "r" ((uint8_t)(__BOOT_LOCK_BITS_SET)), \
00493 "z" ((uint16_t)(address)) \
00494 ); \
00495 __result; \
00496 }))
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00508
00509 #define __BOOT_SIGROW_READ (_BV(__SPM_ENABLE) | _BV(SIGRD))
00510
00511 #define boot_signature_byte_get(addr) \
00512 (__extension__({ \
00513 uint8_t __result; \
00514 __asm__ __volatile__ \
00515 ( \
00516 "sts %1, %2\n\t" \
00517 "lpm %0, Z" "\n\t" \
00518 : "=r" (__result) \
00519 : "i" (_SFR_MEM_ADDR(__SPM_REG)), \
00520 "r" ((uint8_t)(__BOOT_SIGROW_READ)), \
00521 "z" ((uint16_t)(addr)) \
00522 ); \
00523 __result; \
00524 }))
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00587 #if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
00588 || defined(__AVR_ATmega323__)
00589
00590
00591 #define boot_page_fill(address, data) __boot_page_fill_alternate(address, data)
00592 #define boot_page_erase(address) __boot_page_erase_alternate(address)
00593 #define boot_page_write(address) __boot_page_write_alternate(address)
00594 #define boot_rww_enable() __boot_rww_enable_alternate()
00595 #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set_alternate(lock_bits)
00596
00597 #elif (FLASHEND > USHRT_MAX)
00598
00599
00600 #define boot_page_fill(address, data) __boot_page_fill_extended(address, data)
00601 #define boot_page_erase(address) __boot_page_erase_extended(address)
00602 #define boot_page_write(address) __boot_page_write_extended(address)
00603 #define boot_rww_enable() __boot_rww_enable()
00604 #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
00605
00606 #else
00607
00608
00609 #define boot_page_fill(address, data) __boot_page_fill_normal(address, data)
00610 #define boot_page_erase(address) __boot_page_erase_normal(address)
00611 #define boot_page_write(address) __boot_page_write_normal(address)
00612 #define boot_rww_enable() __boot_rww_enable()
00613 #define boot_lock_bits_set(lock_bits) __boot_lock_bits_set(lock_bits)
00614
00615 #endif
00616
00617
00618
00619
00620
00621
00622 #define boot_page_fill_safe(address, data) \
00623 do { \
00624 boot_spm_busy_wait(); \
00625 eeprom_busy_wait(); \
00626 boot_page_fill(address, data); \
00627 } while (0)
00628
00629
00630
00631
00632
00633
00634 #define boot_page_erase_safe(address) \
00635 do { \
00636 boot_spm_busy_wait(); \
00637 eeprom_busy_wait(); \
00638 boot_page_erase (address); \
00639 } while (0)
00640
00641
00642
00643
00644
00645
00646 #define boot_page_write_safe(address) \
00647 do { \
00648 boot_spm_busy_wait(); \
00649 eeprom_busy_wait(); \
00650 boot_page_write (address); \
00651 } while (0)
00652
00653
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00657
00658 #define boot_rww_enable_safe() \
00659 do { \
00660 boot_spm_busy_wait(); \
00661 eeprom_busy_wait(); \
00662 boot_rww_enable(); \
00663 } while (0)
00664
00665
00666
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00669
00670 #define boot_lock_bits_set_safe(lock_bits) \
00671 do { \
00672 boot_spm_busy_wait(); \
00673 eeprom_busy_wait(); \
00674 boot_lock_bits_set (lock_bits); \
00675 } while (0)
00676
00677 #endif