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wdt.h

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00001 /* Copyright (c) 2002, 2004 Marek Michalkiewicz
00002    Copyright (c) 2005, 2006, 2007 Eric B. Weddington
00003    All rights reserved.
00004 
00005    Redistribution and use in source and binary forms, with or without
00006    modification, are permitted provided that the following conditions are met:
00007 
00008    * Redistributions of source code must retain the above copyright
00009      notice, this list of conditions and the following disclaimer.
00010 
00011    * Redistributions in binary form must reproduce the above copyright
00012      notice, this list of conditions and the following disclaimer in
00013      the documentation and/or other materials provided with the
00014      distribution.
00015 
00016    * Neither the name of the copyright holders nor the names of
00017      contributors may be used to endorse or promote products derived
00018      from this software without specific prior written permission.
00019 
00020   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00021   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00022   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00023   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
00024   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00025   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00026   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00027   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00028   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00029   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00030   POSSIBILITY OF SUCH DAMAGE. */
00031 
00032 /* $Id: wdt.h 2211 2011-02-14 14:04:25Z aboyapati $ */
00033 
00034 /*
00035    avr/wdt.h - macros for AVR watchdog timer
00036  */
00037 
00038 #ifndef _AVR_WDT_H_
00039 #define _AVR_WDT_H_
00040 
00041 #include <avr/io.h>
00042 #include <stdint.h>
00043 
00044 /** \file */
00045 /** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
00046     \code #include <avr/wdt.h> \endcode
00047 
00048     This header file declares the interface to some inline macros
00049     handling the watchdog timer present in many AVR devices.  In order
00050     to prevent the watchdog timer configuration from being
00051     accidentally altered by a crashing application, a special timed
00052     sequence is required in order to change it.  The macros within
00053     this header file handle the required sequence automatically
00054     before changing any value.  Interrupts will be disabled during
00055     the manipulation.
00056 
00057     \note Depending on the fuse configuration of the particular
00058     device, further restrictions might apply, in particular it might
00059     be disallowed to turn off the watchdog timer.
00060 
00061     Note that for newer devices (ATmega88 and newer, effectively any
00062     AVR that has the option to also generate interrupts), the watchdog
00063     timer remains active even after a system reset (except a power-on
00064     condition), using the fastest prescaler value (approximately 15
00065     ms).  It is therefore required to turn off the watchdog early
00066     during program startup, the datasheet recommends a sequence like
00067     the following:
00068 
00069     \code
00070     #include <stdint.h>
00071     #include <avr/wdt.h>
00072 
00073     uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
00074 
00075     void get_mcusr(void) \
00076       __attribute__((naked)) \
00077       __attribute__((section(".init3")));
00078     void get_mcusr(void)
00079     {
00080       mcusr_mirror = MCUSR;
00081       MCUSR = 0;
00082       wdt_disable();
00083     }
00084     \endcode
00085 
00086     Saving the value of MCUSR in \c mcusr_mirror is only needed if the
00087     application later wants to examine the reset source, but in particular, 
00088     clearing the watchdog reset flag before disabling the
00089     watchdog is required, according to the datasheet.
00090 */
00091 
00092 /**
00093    \ingroup avr_watchdog
00094    Reset the watchdog timer.  When the watchdog timer is enabled,
00095    a call to this instruction is required before the timer expires,
00096    otherwise a watchdog-initiated device reset will occur. 
00097 */
00098 
00099 #define wdt_reset() __asm__ __volatile__ ("wdr")
00100 
00101 
00102 #if defined(WDP3)
00103 # define _WD_PS3_MASK       _BV(WDP3)
00104 #else
00105 # define _WD_PS3_MASK       0x00
00106 #endif
00107 
00108 #if defined(WDTCSR)
00109 #  define _WD_CONTROL_REG     WDTCSR
00110 #else
00111 #  define _WD_CONTROL_REG     WDTCR
00112 #endif
00113 
00114 #if defined(WDTOE)
00115 #define _WD_CHANGE_BIT      WDTOE
00116 #else
00117 #define _WD_CHANGE_BIT      WDCE
00118 #endif
00119 
00120 
00121 /**
00122    \ingroup avr_watchdog
00123    Enable the watchdog timer, configuring it for expiry after
00124    \c timeout (which is a combination of the \c WDP0 through
00125    \c WDP2 bits to write into the \c WDTCR register; For those devices 
00126    that have a \c WDTCSR register, it uses the combination of the \c WDP0 
00127    through \c WDP3 bits).
00128 
00129    See also the symbolic constants \c WDTO_15MS et al.
00130 */
00131 
00132 
00133 #if defined(__AVR_ATxmega16A4__) \
00134 || defined(__AVR_ATxmega16D4__) \
00135 || defined(__AVR_ATxmega32A4__) \
00136 || defined(__AVR_ATxmega32D4__) \
00137 || defined(__AVR_ATxmega32X1__) \
00138 || defined(__AVR_ATxmega64A1U__) \
00139 || defined(__AVR_ATxmega64A3__) \
00140 || defined(__AVR_ATxmega64D3__) \
00141 || defined(__AVR_ATxmega128A1__) \
00142 || defined(__AVR_ATxmega128A1U__) \
00143 || defined(__AVR_ATxmega128A3__) \
00144 || defined(__AVR_ATxmega128B1__) \
00145 || defined(__AVR_ATxmega128D3__) \
00146 || defined(__AVR_ATxmega192A3__) \
00147 || defined(__AVR_ATxmega192D3__) \
00148 || defined(__AVR_ATxmega256A3__) \
00149 || defined(__AVR_ATxmega256D3__) \
00150 || defined(__AVR_ATxmega256A3B__) \
00151 || defined(__AVR_ATxmega256A3BU__)
00152 
00153 /*
00154     wdt_enable(WDT_PER_8KCLK_gc);
00155 */
00156 #define wdt_enable(value) \
00157 __asm__ __volatile__ ( \
00158     "in __tmp_reg__, %0"  "\n\t" \
00159     "out %1, %3"          "\n\t" \
00160     "sts %2, %4"          "\n\t" \
00161     "wdr"                 "\n\t" \
00162     "out %0, __tmp_reg__" "\n\t" \
00163     : \
00164     : "M" (_SFR_MEM_ADDR(RAMPD)), \
00165       "M" (_SFR_MEM_ADDR(CCP)), \
00166       "M" (_SFR_MEM_ADDR(WDT_CTRL)), \
00167       "r" ((uint8_t)0xD8), \
00168       "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | value)) \
00169     : "r0" \
00170 )
00171 
00172 
00173 #elif defined(__AVR_AT90CAN32__) \
00174 || defined(__AVR_AT90CAN64__) \
00175 || defined(__AVR_AT90CAN128__) \
00176 || defined(__AVR_AT90PWM1__) \
00177 || defined(__AVR_AT90PWM2__) \
00178 || defined(__AVR_AT90PWM216__) \
00179 || defined(__AVR_AT90PWM2B__) \
00180 || defined(__AVR_AT90PWM3__) \
00181 || defined(__AVR_AT90PWM316__) \
00182 || defined(__AVR_AT90PWM3B__) \
00183 || defined(__AVR_AT90PWM161__) \
00184 || defined(__AVR_AT90PWM81__) \
00185 || defined(__AVR_AT90USB1286__) \
00186 || defined(__AVR_AT90USB1287__) \
00187 || defined(__AVR_AT90USB162__) \
00188 || defined(__AVR_AT90USB646__) \
00189 || defined(__AVR_AT90USB647__) \
00190 || defined(__AVR_AT90USB82__) \
00191 || defined(__AVR_ATmega1280__) \
00192 || defined(__AVR_ATmega1281__) \
00193 || defined(__AVR_ATmega1284P__) \
00194 || defined(__AVR_ATmega128RFA1__) \
00195 || defined(__AVR_ATmega164__) \
00196 || defined(__AVR_ATmega164A__) \
00197 || defined(__AVR_ATmega164P__) \
00198 || defined(__AVR_ATmega165__) \
00199 || defined(__AVR_ATmega165A__) \
00200 || defined(__AVR_ATmega165P__) \
00201 || defined(__AVR_ATmega168__) \
00202 || defined(__AVR_ATmega168A__) \
00203 || defined(__AVR_ATmega168P__) \
00204 || defined(__AVR_ATmega169__) \
00205 || defined(__AVR_ATmega169A__) \
00206 || defined(__AVR_ATmega169P__) \
00207 || defined(__AVR_ATmega169PA__) \
00208 || defined(__AVR_ATmega16HVA__) \
00209 || defined(__AVR_ATmega16HVA2__) \
00210 || defined(__AVR_ATmega16HVB__) \
00211 || defined(__AVR_ATmega16HVBREVB__) \
00212 || defined(__AVR_ATmega16M1__) \
00213 || defined(__AVR_ATmega16U2__) \
00214 || defined(__AVR_ATmega16U4__) \
00215 || defined(__AVR_ATmega2560__) \
00216 || defined(__AVR_ATmega2561__) \
00217 || defined(__AVR_ATmega324__) \
00218 || defined(__AVR_ATmega324A__) \
00219 || defined(__AVR_ATmega324P__) \
00220 || defined(__AVR_ATmega324PA__) \
00221 || defined(__AVR_ATmega325__) \
00222 || defined(__AVR_ATmega325A__) \
00223 || defined(__AVR_ATmega325P__) \
00224 || defined(__AVR_ATmega325PA__) \
00225 || defined(__AVR_ATmega3250__) \
00226 || defined(__AVR_ATmega3250A__) \
00227 || defined(__AVR_ATmega3250P__) \
00228 || defined(__AVR_ATmega3250PA__) \
00229 || defined(__AVR_ATmega328__) \
00230 || defined(__AVR_ATmega328P__) \
00231 || defined(__AVR_ATmega329__) \
00232 || defined(__AVR_ATmega329A__) \
00233 || defined(__AVR_ATmega329P__) \
00234 || defined(__AVR_ATmega329PA__) \
00235 || defined(__AVR_ATmega3290__) \
00236 || defined(__AVR_ATmega3290A__) \
00237 || defined(__AVR_ATmega3290P__) \
00238 || defined(__AVR_ATmega3290PA__) \
00239 || defined(__AVR_ATmega32C1__) \
00240 || defined(__AVR_ATmega32HVB__) \
00241 || defined(__AVR_ATmega32HVBREVB__) \
00242 || defined(__AVR_ATmega32M1__) \
00243 || defined(__AVR_ATmega32U2__) \
00244 || defined(__AVR_ATmega32U4__) \
00245 || defined(__AVR_ATmega32U6__) \
00246 || defined(__AVR_ATmega406__) \
00247 || defined(__AVR_ATmega48__) \
00248 || defined(__AVR_ATmega48A__) \
00249 || defined(__AVR_ATmega48PA__) \
00250 || defined(__AVR_ATmega48P__) \
00251 || defined(__AVR_ATmega640__) \
00252 || defined(__AVR_ATmega644__) \
00253 || defined(__AVR_ATmega644A__) \
00254 || defined(__AVR_ATmega644P__) \
00255 || defined(__AVR_ATmega644PA__) \
00256 || defined(__AVR_ATmega645__) \
00257 || defined(__AVR_ATmega645A__) \
00258 || defined(__AVR_ATmega645P__) \
00259 || defined(__AVR_ATmega6450__) \
00260 || defined(__AVR_ATmega6450A__) \
00261 || defined(__AVR_ATmega6450P__) \
00262 || defined(__AVR_ATmega649__) \
00263 || defined(__AVR_ATmega649A__) \
00264 || defined(__AVR_ATmega6490__) \
00265 || defined(__AVR_ATmega6490A__) \
00266 || defined(__AVR_ATmega6490P__) \
00267 || defined(__AVR_ATmega649P__) \
00268 || defined(__AVR_ATmega64C1__) \
00269 || defined(__AVR_ATmega64HVE__) \
00270 || defined(__AVR_ATmega64M1__) \
00271 || defined(__AVR_ATmega88__) \
00272 || defined(__AVR_ATmega88A__) \
00273 || defined(__AVR_ATmega88P__) \
00274 || defined(__AVR_ATmega88PA__) \
00275 || defined(__AVR_ATmega8HVA__) \
00276 || defined(__AVR_ATmega8U2__) \
00277 || defined(__AVR_ATtiny48__) \
00278 || defined(__AVR_ATtiny88__) \
00279 || defined(__AVR_ATtiny87__) \
00280 || defined(__AVR_ATtiny167__) \
00281 || defined(__AVR_AT90SCR100__) \
00282 || defined(__AVR_ATA6289__)
00283 
00284 /* Use STS instruction. */
00285  
00286 #define wdt_enable(value)   \
00287 __asm__ __volatile__ (  \
00288     "in __tmp_reg__,__SREG__" "\n\t"    \
00289     "cli" "\n\t"    \
00290     "wdr" "\n\t"    \
00291     "sts %0,%1" "\n\t"  \
00292     "out __SREG__,__tmp_reg__" "\n\t"   \
00293     "sts %0,%2" "\n\t" \
00294     : /* no outputs */  \
00295     : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
00296     "r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \
00297     "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
00298         _BV(WDE) | (value & 0x07)) ) \
00299     : "r0"  \
00300 )
00301 
00302 #define wdt_disable() \
00303 __asm__ __volatile__ (  \
00304     "in __tmp_reg__, __SREG__" "\n\t" \
00305     "cli" "\n\t" \
00306     "sts %0, %1" "\n\t" \
00307     "sts %0, __zero_reg__" "\n\t" \
00308     "out __SREG__,__tmp_reg__" "\n\t" \
00309     : /* no outputs */ \
00310     : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \
00311     "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
00312     : "r0" \
00313 )
00314 
00315 
00316     
00317 #else  
00318 
00319 /* Use OUT instruction. */
00320 
00321 #define wdt_enable(value)   \
00322     __asm__ __volatile__ (  \
00323         "in __tmp_reg__,__SREG__" "\n\t"    \
00324         "cli" "\n\t"    \
00325         "wdr" "\n\t"    \
00326         "out %0,%1" "\n\t"  \
00327         "out __SREG__,__tmp_reg__" "\n\t"   \
00328         "out %0,%2" \
00329         : /* no outputs */  \
00330         : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
00331         "r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)),   \
00332         "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \
00333             _BV(WDE) | (value & 0x07)) ) \
00334         : "r0"  \
00335     )
00336 
00337 /**
00338    \ingroup avr_watchdog
00339    Disable the watchdog timer, if possible.  This attempts to turn off the 
00340    Enable bit in the watchdog control register. See the datasheet for 
00341    details.
00342 */
00343 #define wdt_disable() \
00344 __asm__ __volatile__ (  \
00345     "in __tmp_reg__, __SREG__" "\n\t" \
00346      "cli" "\n\t" \
00347     "out %0, %1" "\n\t" \
00348     "out %0, __zero_reg__" "\n\t" \
00349     "out __SREG__,__tmp_reg__" "\n\t" \
00350     : /* no outputs */ \
00351     : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \
00352     "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \
00353     : "r0" \
00354 )
00355 
00356 #endif
00357 
00358 
00359 
00360 /**
00361    \ingroup avr_watchdog
00362    Symbolic constants for the watchdog timeout.  Since the watchdog
00363    timer is based on a free-running RC oscillator, the times are
00364    approximate only and apply to a supply voltage of 5 V.  At lower
00365    supply voltages, the times will increase.  For older devices, the
00366    times will be as large as three times when operating at Vcc = 3 V,
00367    while the newer devices (e. g. ATmega128, ATmega8) only experience
00368    a negligible change.
00369 
00370    Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
00371    500 ms, 1 s, 2 s.  (Some devices also allow for 4 s and 8 s.)
00372    Symbolic constants are formed by the prefix
00373    \c WDTO_, followed by the time.
00374 
00375    Example that would select a watchdog timer expiry of approximately
00376    500 ms:
00377    \code
00378    wdt_enable(WDTO_500MS);
00379    \endcode
00380 */
00381 #define WDTO_15MS   0
00382 
00383 /** \ingroup avr_watchdog
00384     See \c WDT0_15MS */
00385 #define WDTO_30MS   1
00386 
00387 /** \ingroup avr_watchdog See
00388     \c WDT0_15MS */
00389 #define WDTO_60MS   2
00390 
00391 /** \ingroup avr_watchdog
00392     See \c WDT0_15MS */
00393 #define WDTO_120MS  3
00394 
00395 /** \ingroup avr_watchdog
00396     See \c WDT0_15MS */
00397 #define WDTO_250MS  4
00398 
00399 /** \ingroup avr_watchdog
00400     See \c WDT0_15MS */
00401 #define WDTO_500MS  5
00402 
00403 /** \ingroup avr_watchdog
00404     See \c WDT0_15MS */
00405 #define WDTO_1S     6
00406 
00407 /** \ingroup avr_watchdog
00408     See \c WDT0_15MS */
00409 #define WDTO_2S     7
00410 
00411 #if defined(__DOXYGEN__) || defined(WDP3)
00412 
00413 /** \ingroup avr_watchdog
00414     See \c WDT0_15MS
00415     Note: This is only available on the 
00416     ATtiny2313, 
00417     ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
00418     ATtiny25, ATtiny45, ATtiny85, 
00419     ATtiny261, ATtiny461, ATtiny861, 
00420     ATmega48, ATmega88, ATmega168,
00421     ATmega48P, ATmega88P, ATmega168P, ATmega328P,
00422     ATmega164P, ATmega324P, ATmega644P, ATmega644,
00423     ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
00424     ATmega8HVA, ATmega16HVA, ATmega32HVB,
00425     ATmega406, ATmega1284P,
00426     AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
00427     AT90PWM81, AT90PWM161,
00428     AT90USB82, AT90USB162,
00429     AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
00430     ATtiny48, ATtiny88.
00431     */
00432 #define WDTO_4S     8
00433 
00434 /** \ingroup avr_watchdog
00435     See \c WDT0_15MS
00436     Note: This is only available on the 
00437     ATtiny2313, 
00438     ATtiny24, ATtiny44, ATtiny84, ATtiny84A,
00439     ATtiny25, ATtiny45, ATtiny85, 
00440     ATtiny261, ATtiny461, ATtiny861, 
00441     ATmega48, ATmega48A, ATmega48PA, ATmega88, ATmega168,
00442     ATmega48P, ATmega88P, ATmega168P, ATmega328P,
00443     ATmega164P, ATmega324P, ATmega644P, ATmega644,
00444     ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
00445     ATmega8HVA, ATmega16HVA, ATmega32HVB,
00446     ATmega406, ATmega1284P,
00447     AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
00448     AT90PWM81, AT90PWM161,
00449     AT90USB82, AT90USB162,
00450     AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
00451     ATtiny48, ATtiny88.
00452     */
00453 #define WDTO_8S     9
00454 
00455 #endif  /* defined(__DOXYGEN__) || defined(WDP3) */
00456    
00457 
00458 #endif /* _AVR_WDT_H_ */

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